1. Field of the Invention
This invention is concerned with a method of manufacturing a semiconductor device and in particular relates to a semiconductor device made using an improved multi-level interconnection layer forming step.
2. Description of the Prior Art
Conventionally the following method has been adopted for forming a multi-level interconnection layer on a semiconductor substrate. This method is explained with reference to FIG. 1 and FIG. 2. First of all, a field oxide film 2 is formed on the surface of a semiconductor substrate 1 to isolate island-shaped elements, and a first Al film is deposited on this oxide film 2. A first interconnection layer 3 is then formed by patterning this Al layer. After this, an insulating film 4 is deposited by the Chemical Vapor Deposition (CVD) Method to provide insulation between the first and second interconnection levels. Next, manufacture of the semiconductor device is completed by forming a second interconnection layer 6 connected through contact holes 5 with first interconnection layer 3 on insulating film 4 by sputtering a second Al film onto the entire surface and patterning.
However, with this conventional method as described above, device reliability is adversely affected by poor step coverage of the second Al film on the inside of contact holes 5. Furthermore, in order to prevent poor step coverage of contact holes 5, fringes 7 of second interconnection layer 6 have to be provided around contact holes 5. The interconnection density which can be attained is lowered by the need to form these fringes 7.
The above leads to the development of a multi-level interconnection technique wherein first and second interconnection levels are connected using pillars, as announced by R. E. Oakley et al, "IEEE, VLSI Multilevel Interconnection Conference, 1984". This technique will now be described, with reference to FIGS. 3(a) to (f) and FIG. 4.
A three-layer film is formed as shown in FIG. 3(a). First of all, a field oxide film 12 is formed to isolate island elements on the surface of a semiconductor substrate 11. Then an Al film 13 of thickness about 1 micron is deposited on oxide film 12 and constitutes a first interconnection layer. A Cr film 14 constituting an etch stop layer and an Al film 15 of thickness about 1 micron that is to constitute the pillars are successively deposited. After this, the three-layer film is patterned in the shape of the first interconnection layer, forming (nearest field oxide film 12), a first interconnection layer 16 consisting of Al, a Cr pattern 17, and an Al pattern 18 (see FIG. 3(b)).
Next, as shown in FIG. 3(c), a resist pattern 19 is formed by photolithography on those parts which are destined to become the pillars of Al pattern 18. After this, using resist pattern 19 as a mask, exposed Al pattern 18 and Cr pattern 17 are removed by etching. Resist pattern 19 itself is then removed, so that pillars 20 consisting of Al are formed on first interconnection layer 16 with Cr pattern 17 in between (see FIG. 3(d) and FIG. 4). FIG. 4 is a perspective view of FIG. 3(d). In this step, Cr pattern 17 and Al pattern 18 are removed from the other parts of first interconnection layer 16, which are adjacent the parts of first interconnection layer 2 where pillars 20 are formed.
Next, a liquid organic material such as polyimide is applied over the whole surface by spinning, to form an insulating film 21. The substrate surface is then planarized (see FIG. 3(e)) by applying a photoresist 22 on top of this insulating film 21. Following this, the tops of pillars 20 are exposed from photoresist film 22 and polyimide insulating film 21 by the etch-back technique. After this, a second interconnection layer 23 connected with first interconnection layer 16 by means of pillars 20 is formed (see FIG. 3(f)) by sputtering a second Al film onto the whole surface, and patterning.
The method of realizing multi-level interconnections using pillars 20 as described above enables higher circuit integration densities to be achieved than when multi-level interconnections are formed using contact holes, as hitherto. Such a method is, however, subject to the following problems.
(1) Since three metallic layers are involved, both film formation and etching are operationally inconvenient and the production steps are complicated. PA1 (2) Fine patterning of the metal layers is difficult. Specifically, in order to etch the three-layer Al/Cr/Al construction, the reactive ion etching (RIE) technique is adopted, but the etching selectivity of the Al and photoresist cannot be made very high and is in fact usually about 2 to 3. As a result, patterning an Al film having a film thickness of approximately 2 micron using the photoresist pattern as a mask is difficult. Furthermore, when RIE of the Al is performed using a gas such as Cl system, after-corrosions tend to occur. This phenomenon is particularly marked with a three-layer structure as described above. PA1 (3) Since an organic material such as a polyimide is used for the insulating film, water absorption by this organic material causes corrosion of the metal interconnections, resulting in polarization and causing deterioration of device characteristics or cracks, due to the large stresses. In particular, various reliability problems arise with MOS devices.